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Sheet目录3881

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PIC18FXX39

DS30485A-page 270

Preliminary

2002 Microchip Technology Inc.

23.3.3

TIMING DIAGRAMS AND SPECIFICATIONS

FIGURE 23-5:

EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)

TABLE 23-4:

EXTERNAL CLOCK TIMING REQUIREMENTS

TABLE 23-5:

PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2 TO 5.5V)

OSC1

CLKO

Param.

No.

Symbol

Characteristic

Min

Max

Units

Conditions

FOSC

External CLKI Frequency(1)

Oscillator Frequency(1)

MHz

EC, ECIO, -40

°C to +85°C

MHz

EC, ECIO, +85

°C to +125°C

MHz

HS osc

MHz

HS + PLL osc, -40

°C to +85°C

6.25

MHz

HS + PLL osc, +85

°C to +125°C

TOSC

External CLKI Period(1)

Oscillator Period(1)

—

EC, ECIO, -40

°C to +85°C

—

EC, ECIO, +85

°C to +125°C

250

HS osc

100

250

HS + PLL osc, -40

°C to +85°C

160

250

HS + PLL osc, +85

°C to +125°C

TCY

Instruction Cycle Time(1)

100

—

TCY = 4/FOSC, -40

°C to +85°C

160

—

TCY = 4/FOSC, +85

°C to +125°C

TosL,

TosH

External Clock in (OSC1)

High or Low Time

—

HS osc

4TosR,

TosF

External Clock in (OSC1)

Rise or Fall Time

—7.5

HS osc

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period for all configurations

except PLL. All specified values are based on characterization data for that particular oscillator type under

standard operating conditions with the device executing code. Exceeding these specified limits may result in

an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to

operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input

is used, the “max.” cycle time limit is “DC” (no clock) for all devices.

Param

No.

Sym

Characteristic

Min

Typ

Max

Units

Conditions

—FOSC Oscillator Frequency Range

—

MHz HS mode only

—FSYS

On-Chip VCO System Frequency

—

MHz HS mode only

—trc

PLL Start-up Time (Lock Time)

—

CLK CLKO Stability (Jitter)

-2

—

Data in “Typ” column is at 5V, 25

°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

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